The present invention relates to a method of electro-mechanical polishing (EMP) surfaces, especially surfaces of platinum container structures, during semiconductor device fabrication.
As the dimensions of semiconductor devices continue to decrease, there is a need for high resolution patterning of device features. The need for smaller surface area for components, such as capacitors or transistors, along with the requirement to maintain high-reliability electrical connections, have led researchers to seek new materials and methods for fabricating semiconductor components.
For example, promising candidates for materials for capacitor electrodes used in integrated circuits memory structures include noble metals, i.e., platinum (Pt), palladium (Pd), iridium (Ir), ruthenium (Ru), rhodium (Rh), osmium (Os), silver (Ag) and gold (Au), as wells as their oxides, e.g., ruthenium oxide (RuO2), iridium oxide (IrO2) or osmium oxide (OsO2). The above-mentioned noble metals, of which platinum (Pt) is the most common, are all physically and chemically similar. They are either relatively stable metals or form conductive oxides. Their capacitance remains constant even when exposed to oxidizing or reducing atmospheres common to semiconductor fabrication. These metals are also resistant to hydrogen damage and do not affect the polarization of dielectric layers after annealing at high temperatures.
Recently, particular attention has been given to using platinum (Pt) for electrodes mainly because platinum has a very low reactivity and is inert to oxidation, thus preventing electrode oxidation which decreases a capacitor""s capacitance. Platinum also has a high electrical conductivity and a lower leakage current than that of other electrode materials, such as for example, ruthenium oxide or poly-silicon. Further, platinum has a high work function. Work function is an important feature of an electrode material for a DRAM capacitor and is a measure of the energy required to remove one electron from the metal. Advanced DRAM capacitors are characterized by a dominant current leakage mechanism, known as the Schottky emission from the electrode into the dielectric so that metals with high work functions, like platinum, produce less current leakage.
The use of platinum as the material of choice for capacitor electrodes, however, poses significant problems. One problem arises from the difficulty of etching and/or polishing platinum and the corresponding need to precisely etch the platinum into the shape of the desired capacitor electrode. The etching process, which is repeated many times in the formation of semiconductor devices, typically employs at least one chemical etchant that reacts with, and removes, the film or layer that is etched. Noble metals such as platinum, however, are not highly reactive with conventional chemical etchants. Consequently, noble metals require specialized etching methods and/or highly-reactive chemical etchants in the etching process.
Two methods are currently being used to etch platinum. The first method is isotropic etching, such as wet etching with aqua regia (mix ratio of concentrated hydrochloric acid: concentrated nitric acid: water=3:1:4). This wet etching, however, offers a very low degree of precision. Consequently, wet etching is not accurate enough for many fine pattern processes, such as patterning DRAM devices, rendering it difficult to perform submicron patterning of platinum electrodes.
The second method is anisotropic etching, such as ion beam milling, under which ions, e.g., argon ions, are generated by a magnetically confined RF or DC plasma and bombard an exposed platinum surface. While the ion beam milling process is used to define and form high resolution patterns from a blanket platinum layer, this process is typically not selective to many masking materials as well as to the layers underlying the platinum layer. Further, ion beam milling processing removes most materials at about the same rate, making process control very difficult as the ion beam may remove material underlying a protective mask as well as unwanted material.
Accordingly, there is a need and desire for an improved method of patterning metal surfaces during the formation of semiconductor device components, e.g., capacitors. There is also a need and desire for high-resolution patterning of noble metal layers, e.g., platinum, during the formation of a lower capacitor electrode, as well as a method of increasing the processing accuracy in etching a noble metal surface.
The present invention provides a method for patterning metal surfaces employed in the formation of various semiconductor device components, such as capacitors, as well as a method for increasing processing accuracy in polishing metal surfaces.
In an exemplary embodiment, a metal surface is patterned by electro-mechanical polishing to form the bottom electrode of a DRAM capacitor. To form the bottom electrode, an insulating layer is formed over a contact plug that is in electrical contact with a transistor gate stack. A container opening is formed in the insulating layer to expose the contact plug. A metal layer is deposited in the container structure and on the exposed surface of the insulating layer. A photoresist layer is deposited over the metal layer, forming a plug in the container. The photoresist layer is chemically mechanically polished to expose the surface of the metal layer outside the container. The surface of the metal layer outside the container structure is electro-mechanically polished against a second surface while submersed in an electrolytic bath. The metal surface and polishing pad are connected to an electrical source and a current is supplied to them during polishing. The metal surface is polished until the metal outside the container is removed. The photoresist is removed from the container exposing the surface of the metal surface inside the container. In an exemplary embodiment, platinum is used as the metal layer.